What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Video IP Design Verification Engineer

The Role:

We, the VCN (Video Codec Next) IP team, are based in Markham, ON, Canada. We focus on video codec IP development for AMD SOCs with leading ASIC technology. We are looking for a self-motivated, experienced (MTS level) verification engineer in the Folsom, California area to complement our team to develop world class video solutions verified to the highest standards.

The Person:

You are expected to actively collaborate with various team members to understand design requirements, drive block-level verification, support IP level integration and verification, and pursue functional and code coverage closure linked back to requirements throughout the design cycle. Solid technical skills, a self-driven attitude, and excellent communication skills especially remotely are key factors to be successful in our organization.

Key Responsibilities:

• Draft block-level verification plan with functional coverage specification.
• Construct block-level testbenches using UVM.
• Devise and implement block-level tests, and manage regression suites with performance and scalability considerations
• Triage test run failures and provide debug support to design engineers to isolate the causes.
• Actively drive simulation throughput profiling and use state-of-the-art practices to help optimize regression turnaround times.
• Own verification of the design across multiple abstractions and views, including C-model simulation, RTL simulation and formal verification.
• Ensure the design can meet performance targets with accurate modeling of interface protocol behavior in the block-level testbenches in aligned with IP level behavior with top-down constraints.
• Conduct coverage analysis, profiling, and reporting, and augment test suites towards coverage improvements and sign-off.
• Support IP-level feature integration and bring-up of RTL blocks and assist in IP-level simulation debug.

Preferred Experience:

• Minimum 7 years of solid ASIC/FPGA design verification experience.
• Rich knowledge of ASIC design flow from specification to implementation and verification.
• Well-versed in UVM. 
• Strong in SystemC, C++/C programming.
• Solid knowledge of Verilog RTL design.
• Experience with HLS flow in complex design implementation and verification is a definite asset
• Familiar with simulation CAD tools including coverage reporting and profiling.
• Handy in Linux scripting languages such as Perl, Python, Ruby and/or shell languages.
• Solid problem-solving skills.
• Prior team or technical leadership, or mentorship, are great value-added assets
• Excellent team player and communicator
• Basic video codec knowledge is a definite plus.

Academic Credentials:

Minimum Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering.