What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Job Title: Summer 2022 Intern Silicon Design Engineer

Job Description: Data Fabric Front End Design

Data Fabric Front-End Design Engineer

THE ROLE:

This is a front-end design engineering position on AMD’s Data Fabric IP. The Data Fabric is the high-bandwidth, high performance, fabric network logic that ties together all the IPs on an SOC. Every product that AMD sells has its own custom-designed Data Fabric, so this role gives an engineer the opportunity to work on a broad array of products that address a variety of markets, including traditional servers, high performance computing, client desktop and laptop PCs, machine intelligence, graphics, console gaming, embedded, and customer-specific applications. It is a challenging position that involves working at a fast pace of innovation on the cutting edge of technology. Come join the AMD team!

THE PERSON:

The candidate should be able to work cooperatively with a talented global team and use his or her engineering skills to solve novel problems and optimize designs and flows.

KEY RESPONSIBILITIES:

• Work with the Data Fabric architects and the chip floorplanning team to develop a custom Data Fabric topology
• Synthesize Data Fabric IP using Synopsys tools and work with the micro-architects to ensure the design components meet the project’s area, power, and performance goals
• Provide feedback to RTL team to resolve timing, power, area, LINT, DFT, and cross-clock-domain issues.
• Provide interface to integrate IP blocks into the SOC and resolve the same types of power, timing, area, and formal equivalence checking at the chip level.
• Analyze design power and devise improvements through architectural or flow optimizations

PREFERRED EXPERIENCE:

• Extensive working knowledge, gained through multiple tapeouts, of the latest generation of Synopsys design tools, including Design Compiler NXT, Formality, Power Compiler, PrimeTime, Fusion Compiler, and IC Compiler II
• A proven understanding of computer architecture 
• Knowledge of high performance interconnection logic and networks is a plus

ACADEMIC CREDENTIALS:

• MS degree in Computer Engineering preferred