What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Sr. PD Engineer

The Role:

The main job will be to perform tasks within the Physical design team to deliver graphics hard-ip to internal SOC customers.   

The Person:

Our team is a diverse group of engineers. To be successful in this role, you should have strong time management and ability to adapt to AMD schedules.  You are a highly motivated self-started with excellent communication, analytical and problem-solving skills.  In addition, you are a strong team player and possess the ability to provide mentorship and guidance to peers and more junior level staff.

Key Responsibilities:

• Tasks could include RTL Synthesis, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off at block and full-chip level
• Generate and validate timing constraints and SDC constraints at block and full-chip level
• Drive timing closure across multiple modes, timing corners and VF curves
• Identify complex technical problems, break them down, summarize multiple possible solutions, and drive closure
• Drive and hands-on flow development, scripting and process improvements as needed
• Participate in technical and schedule discussions with peers and managers globally

Preferred experience:

• Knowledge of timing corners/modes, process variations and signal integrity related issues
• Clear understanding of Chip power-on/debug/test, clocks and reset methods
• Hands on experience in timing/SDC constraints generation and management
• Understanding tradeoff of mode merging, timing corners optimizations and Voltage-frequency curves
• Proficient in scripting languages (TCL and Perl)

• Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools
• Should be familiar with design robustness and additional signoff checks like CDC checks

• Working knowledge of industry standard EDA tools on latest process technologies

Academic Credentials:

• Bachelor/Undergraduate Computer Engineering, Electrical Engineering; Masters degree preferred

Location:

• Roseville/Folsom, Santa Clara, San Diego, Orlando