What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

SMTS  Silicon Design Engineer  127683 

The Role:

Work in an advanced design data base set up, take on various verification tasks independently and problem solving whenever needed. IP level Test plan writing and test case/scenario review as needed. Help in Regression coverage tracking and dbg, so candidate needs to be efficient in reading complicated design style SystemVerilog codes. Leading IP level formal/property verification challenges confidently. We are a cloe work together team, so you need to feel comfortable working with people and communicate clearly. As a senior IP team memebetr, you may have to help various SOC requests for debug and support as needed.

Responsibilites:

Familiarity with modern Computer Architecture is a must.

SystemVerilog, UVM and/or C/C++ efficiency is a must.

Previous DV coverage analysis/regression handling/debug experiences is a plus.

Previous formal/proprty verification experience is a plus.

Linux usage experience is a must. Fluent in Makefile, and/or modern scripting languages is a plus.

Efficiency of reading RTL style Verilog design or prior design experience is a major plus

Experience/Education:

Minimum 6 years in logic design verification (or 10 years mixed with logic design)

BSEE/CE/CS with solid computer architecture course work, MSEE/CE/CS preferred.