What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

This JD is a reference from a FT DV Engineer. All NCG hires will go through a basic training assignment first before further assignment.

Silicon Design Verification Engineer

The role:

A Design Verification Engineering role in our System Management Unit (SMU) IP team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our verification engineers will work on block level functional verification and its closure, and/or on subsystem level integration and verification for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications.

The person:

A talented hardware/firmware co-design/verification engineer with strong records of technical ownership and execution to drive block level IP and/or MP subsystems design and verification assignments to completion.  A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

Key responsibilities:

• Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure
• Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology and C-DPI directed test methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests
• Triage regressions, debug simulations, analyze coverage, and work/resolve technical issues with design, verification, and other teams and achieve verification closure
• Participate in subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems
• Debug and solve integration issues with SoC Integration and SoC DV teams

Preferred experience:

• BSc with a minimum of 5 years of relevant experience; or MSc with a minimum of 3 years; or PhD in a directly related research area and a minimum of 1 year
• Proven understanding of MP subsystem architecture and of FPGA based simulation or emulation methodology
• Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile)
• Excellent knowledge about state-of-art verification methodology and best practices, UVM, and C-DPI
• Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
• Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc.

Academic credentials:

• Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
• Master's Degree preferred