Microsoft Cloud Hardware Infrastructure Engineering (CHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. CHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Skype, OneDrive and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.

Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high energy engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and HW infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud AI & Advanced Systems Engineering (CAASE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale, and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a strong passion for customer focused solutions, insight, and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

Microsoft is seeking a highly motivated FPGA or ASIC design engineer to help build, test, and deploy hardware accelerators for next generation networking, storage, and AI/ML applications. Azure has the largest deployment of cloud FPGAs in the world. Candidates should be able to drive projects with both hardware and software teams, and both inside and outside of Microsoft. Microsoft products touch the lives of millions of users daily, and this is a unique opportunity for hardware developers to see their RTL code go to production within weeks instead of years. Come help build one of the few truly hyperscale global clouds with innovations possible at every level of the computing stack.

Candidates should have experience architecting, implementing and debugging interfaces such as Ethernet, PCIe and DRAM using SystemVerilog in FPGA architectures. Candidates should also have experience leading small teams in technical tasks, and coordinating across organizational boundaries to deliver solutions on time and on budget. Candidates should have a strong desire to learn how software solutions can be used to develop FPGA and/or ASIC solutions for Microsoft’s next generation of cloud servers and applications. The candidate will contribute to a team developing IP for both FPGAs and ASICs. The successful candidate will be a strong communicator, creative, a critical thinker, and able to analyze and resolve complex issues.

#azurehwjobs #OCP2021

Responsibilities

Design, propose and oversee the analysis/evaluation of hardware architectures

Design and code RTL modules written in Verilog / SystemVerilog and targeting FPGAs

Simulate and perform hardware-based testing, debug, and verification of FPGA designs

Scripting and basic software development in support of hardware design

Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment

Handle a DevOps role with occasional on-call responsibilities for resolving customer issues in production

Qualifications

Basic Qualifications:

B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science

10+ years of experience with software and hardware systems design, experience analyzing and improving RTL hardware performance and area as well as lab bringup.

FPGA development environment tools expertise, including design, implementation and debug

Strong knowledge with RTL programming languages Verilog/SystemVerilog (preferred), or VHDL

Ability to read and write code in C, C++, C#, SystemC, Powershell and/or Python

Preferred Qualifications:

Developing and deploying cloud applications for cloud hardware (NICs, GPUs, etc) highly preferred

Deep experience with FPGA programming including timing closure, resource management, and using IP libraries highly preferred

Experience with Agile development methodologies and DevOps

Experience leading projects across organizational boundaries

Experience in technical leadership of small teams

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. 

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.  We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.