What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Video Codec Staff Design Engineer

The Role:

We, the VCN (Video Codec Next) IP team, are based in Markham, ON, Canada! We focus on video codec IP development for AMD SOCs with leading ASIC technology. We are looking for a self-motivated, experienced (MTS level) design engineer in the Folsom, CA, area to complement our team to develop world-class video solutions.

The Person:

You are encouraged to actively collaborate with various team members to understand design requirements, drive block level development, IP level bring-up, timing/area/performance trade-offs throughout the design cycle. Proven technical skill, and excellent communication skill working in remote teams are key factors to make you successful in this group.

Key Responsibilities:

• Draft block level design requirements and micro-architecture specifications.
• Perform block level modeling, RTL/HLS implementation.
• Define block programming model and interact with firmware/software team to bring-up functionality at IP and SOC levels.
• Perform design metrics checks such as LINT, CDC, synthesis, static timing analysis, and power analysis.
• Work with verification engineers to define test plan and functional verification coverage.
• Engage verification closure, including test debug, code coverage and functional coverage review and sign-off.
• Responsible for bug fixes, including engineering change order (ECO) implementation and verification through formal verification.

Preferred Experience:

• Minimum 7 years of proven ASIC/FPGA design and verification experience.
• Rich knowledge about ASIC design flow from specification, implementation, to verification.
• Strong in SystemC, C++/C programming.
• Proven RTL design experience using Verilog.
• Experience using HLS methodology in sophisticated design implementations along with verification skills is an asset
• Familiar with CAD tools of simulation, SystemC to RTL synthesis, RTL to gate synthesis, static timing analysis and formal verification.
• Handy in Linux script languages such as Perl, Python, Ruby or/and shell languages.
• Proven problem solving skill.
• Prior team, technical leadership or mentorship are great valuable assets
• Good teammate and communicator
• Basic video codec knowledge is definitely a plus.

Academic Credentials:

Minimum Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering.

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AMD employees who will be working onsite at an AMD US facility, are encouraged to provide proof of being fully vaccinated against COVID-19 upon their start date. This is for the safety of our employees, and to permit AMD to be prepared in the event the stay on Executive Order 14042: Ensuring Adequate COVID Safety Protocols for Federal Contractors is lifted. AMD is not requiring exemption / accommodation submittals at this time.