What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Mixed Signal DFT Architect

The Role:

We are under tremendous growth at AMD! Come and be a member of the Circuit Technology Team that plays a significant role in ensuring the quality of designs through structured DFT, Automatic Test Pattern Generation (ATPG) and Built-In Self-Test (MBIST) techniques.

The Person:

We are seeking a candidate that has a blend of talents and experiences within DFT. The candidate must have detailed knowledge of DFT basics such as MBIST and scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. We are motivated to find the person with this set of skills!

Key Responsibilities:

• DFT architecture development/definition for Circuit technology IPs (High speed SerDes, memory Phy etc)
• DFT IP development, RTL coding and integration to support functional tests as well as ALL structural tests for the IP, post silicon support
• SDC development and delivery for shift/capture modes
• Compression RTL generation and integration into the DFT wrapper
• Boundary Scan integration into the DFT wrapper
• Ownership of inserting all the test structures (scan wrappers for scan isolation, MBIST, OCCs for test clocking, silicon debug features etc)
• Developing, improving and maintaining scripts and documentation as vital
• Post silicon debug and support

Preferred Experience:

• Experience with test tools such as FastScan and TestKompress
• Strong understanding of industry standard DFT techniques – JTAG, P1500/1687.
• Experience with DFT architecture (scan, test clocking, core wrapping techniques etc), RTL integration, compilation, logic design flow, modeling, RTL-implementation
• Experience with Boundary scan (AC/DC) integration, BSDL development and verification.
• Knowledge of Synthesis basics, scan stitching, Logic Equivalence checks
• Understanding of Compression architecture (Mentor will be preferred), ATPG concepts, timing closure concepts (setup/hold/false/multi-cycle paths etc), sdc understanding
• Proficiency with Industry Standard tool for Scan, ATPG, & MBIST, Programming/Scripting in Perl, Tcl, & Make is desired

Academic Credentials:

• BS/MS in ECE/EEE or equivalent.

Location:

Santa Clara, CA or Boxborough, MA