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Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Design-for-Testability (DFT) Lead Engineer - 115241

The Role:

As a Design-for-Testability (DFT) Lead Engineer, you will lead a team implementing and verifying DFT architecture and features. This will include being the prime interface to and you will meet regularly with other functional team members such as Architects, Physical Designers, CAD Engineers, SoC Design Engineers, Product Engineers and Program Management to ensure successful and timely project completion. You will be responsible for coordinating team resources, schedule alignment, netlist and pattern delivery, ensuring complete and documented handoffs as needed with PD, Verification and Product Validation teams.

Key Responsibilities:

• Lead a small team of DFT engineers for Implementation and verification of DFT architecture and features
• Scan/Jtag/Boundary Scan insertion and ATPG pattern generation
• Memory BIST logic generation, implementation and verification
• ATPG patterns verification with gate level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bringup and enhance yield learning

The Person:

We are looking for a dynamic Lead DFT Engineer to join our growing team; someone who can lead,  who is able to work efficiently within a team environment and drive tasks to completion, all while demonstrating excellent oral, written and interpersonal communication skills!

Skills required:

• Master with at least 6 years or Bachelor with at least 8 years working experience in ASIC DFT area.
• Technical management skills with a small team
• Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, etc)
• Experience with Mentor Testkompress and/or Synopsys Tetramax/DFTMAX
• Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design
• Exposure to Static timing analysis & Timing closure is required.
• Pre-Silicon test planning & validation, engagement with Design teams
• Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies
• Optimization of test flows for increased quality and cost improvement
• Analysis of part failures leading to test coverage and yield improvement
• Analysis of characterization data across PVT
• Must have good communication skills and the ability to work in a worldwide team environment.
• Knowledge & experience of low power concepts, clock gating, power gating is a plus