CAD Power and Timing Methodology Engineer

CAD Power and Timing Methodology Engineer

CAD Power and Timing Methodology Engineer

Job Overview

Location
London, England
Job Type
Full Time Job
Job ID
47500
Date Posted
1 year ago
Recruiter
Helen Josh
Job Views
66

Job Description

What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

CAD Power and Timing Methodology Engineer - 125221

THE ROLE

As a Power and Timing Analysis Engineer at AMD, you will develop new methodologies and flows for the power and timing analysis of AMD's leading edge CPU, GPU, and SoC designs.

The Person

The candidate should have strong analytical thinking and problem-solving skills with excellent attention to details. Must be organized, self-motivated and able to work effectively with teams across world-wide sites. Strong verbal and written communication skills are crucial for driving technical conversations to achieve best in class capabilities that result in optimal power, performance and area in our designs.

Key responsibilities

  • Work closely with design and EDA vendors to maximize the performance, throughput, and QoR of AMD's power and timing analysis flows.
  • Partner with internal teams to optimize turnaround time and design productivity.
  • Write specifications, design, and develop new analysis capabilities which are not available from vendor tools to ensure best-in-class PPA.
  • Enhance reporting of power results and annotation rates to produce data that increase design productivity and confidence in the results.
  • Enhance flows related to mapping of SoC-level simulation/emulation vectors to gate-level switching activity.

Required Experience

  • Bachelor's degree or higher in electrical engineering, computer engineering, or related areas.
  • Experience with power analysis tool such as Synopsys PrimePower.
  • Familiarity with methods for post-route power optimization, timing analysis tools, and gate-level design.
  • Experience with medium to large scale code development/testing and best practices.
  • Experience with Tcl, Linux shell, and Perl or Python.
  • Experience with 14nm and smaller process nodes.

Preferred 

  • Experience with PrimeTime STA.
  • Knowledge of algorithms, data structures, graph theory, statistics.
  • Experience with synthesis and P&R tools.
  • Experience with post-route power optimizations.
  • Experience with version control software like Perforce or Git.
  • Experience with an editor suitable for development like Vi or Emacs, and Linux OS.

Academic credentials

Bachelors or Master's degree in Electrical or Computer Engineering preferred.

Job ID: 47500

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