What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

ASIC IP RTL Design Engineer - 92822

As a member of the Computing and Graphics Semi-Custom Business Unit within AMD, your execution will help bring to life customers' special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more!  

The Role:

As a member of our IP RTL design team, you will take an active role in the lifecycle of digital IP development, resulting in a quality delivery of the IP RTL subsystem to AMD SOCs.  You'll join a tight-knit group that uses top notch tools in leading edge process technologies.  Collaborate with the architecture, SOC design, DFT, verification, and physical design teams for first pass silicon success!

The Person:

We are seeking someone with excellent problem solving, analytical, and debugging skills as well as a strong verbal and written communicator to work with team members across multiple sites. Also, must be a self-starter and able to independently drive tasks to completion!

Key responsibilities:

In this role, you will be responsible for the design of RTL blocks in verilog, which encompasses integration of 3rd party IP as well as custom logic design. You will have the opportunity to contribute to the specification and quality checks (lint, CDC, and power rule checks) of power-gated digital designs. 

• Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC
• Partner with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up

Preferred experience:

• Knowledge and understanding of processor and data fabric architectures
• Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
• 3rd party IP integration
• Power saving techniques, including clock gating and UPF-based power gating
• Detailed understanding of ASIC design flows
• Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
• Clock domain crossing (CDC) tools (0-in)
• Power domain checking tools (VC_LP)
• Strong Unix scripting and utilities (Shell, Perl, TCL, XML, Ruby, makefiles) for analysis and automation
• Background and working knowledge in other aspects of ASIC implementation, such as Synopsys synthesis, timing constraints, PrimeTime static timing analysis, or verification is a plus 
• Background in clocking, reset, power-up sequences and power management is a plus

Academic credentials:

• Bachelor or Master of Science Degree in Electrical or Computer Engineering
• ASIC or IP design experience (outside university) preferred