What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

ASIC IP RTL Design Engineer - Low Power - 116149

The Role:

As a member of our IP RTL design team, you will take an active role in the lifecycle of digital IP development, especially contributing in the area of low power design. Your contributions will result in a quality delivery of the IP RTL subsystem to AMD SOCs. You'll join a tight-knit group that uses top notch tools in groundbreaking process technologies. Collaborate with the architecture, SOC design, DFT, verification, and physical design teams for first pass silicon success!

The Person:

• Excellent problem solving, analytical, and debug skills
• Must be a self-starter and able to independently drive tasks to completion
• Strong verbal and written communication skills to work with team members across multiple sites in multiple geographies

Key Responsibilities:

• Drive new power features roadmap for the IP
• Apply low power design techniques to existing and future logic to meet power targets
• Work with architects to define the power verification strategy
• Design of RTL blocks in Verilog, which encompasses integration of 3rd party IP as well as custom logic design
• Contribute to the specification and quality checks (lint, CDC, and power rule checks) of power-gated digital designs
• Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC
• Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up
• Report IP level power estimation and measurements to leadership

Preferred Experience:

• Understanding of processor and data fabric architectures
• Proficiency in Verilog/System Verilog RTL logic design of high-speed, multi-clock digital designs
• 3rd party IP integration
• Power saving techniques, including clock gating and UPF-based power gating
• Detailed understanding of ASIC design flows
• Power artist & PTPX
• Verilog lint tools (Spyglass) and Verilog simulation tools (VCS)
• Clock domain crossing (CDC) tools (0-in)
• Power domain checking tools (VC_LP)
• Strong Unix scripting and utilities (Shell, Perl, TCL, XML, Ruby, makefiles) for analysis and automation
• Background in clocking, reset, and power-up sequences is a plus

Academic Credentials:

• Bachelor or Master of Science Degree in Electrical or Computer Engineering
• 7 or more years of ASIC or IP design experience (outside university) preferred