ASIC Functional Modeling Verification Engineer

ASIC Functional Modeling Verification Engineer

ASIC Functional Modeling Verification Engineer

Job Overview

Location
London, England
Job Type
Full Time Job
Job ID
39616
Date Posted
1 year ago
Recruiter
Helen Josh
Job Views
33

Job Description

What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

ASIC Functional Modeling Verification Engineer

The Role:

The focus of this role is to plan, create, and maintain the functional verification model used to verify new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.

The Person:

  • An analytical problem solver with problem-solving skills and excellent attention to detail
  • Possesses excellent comprehension, communication, and interpersonal skills
  • Enjoys working in a fast-paced, multi-project team environment using state of the art tools and technology

Key Responsibilities:

  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features being implemented
  • Plan and implement the required changes to the functional model so that the model accurately represents the new and modified hardware
  • Work with the architecture modeling team to incorporate the updated functional model in the performance model
  • Participate in debugging failing verification tests to determine if the root cause is an error in the RTL, verification model, or the test. Fix all identified failures in the verification model.

Preferred Experience:

  • C/C++ programming and debug in a Linux environment
  • Knowledge of ASIC design and functional modeling
  • Graphics pipeline knowledge a plus
  • Proficiency in debugging RTL code using simulation tools a plus
  • Proficient in using UVM testbench a plus
  • Experienced with Verilog, System Verilog a plus

Academic Credentials:

  • BS/MS degree in Electrical Engineering, Computer Engineering, or Computer Science

Location:

This position is located in Orlando, FL or Austin, TX

#LI-DC3

Job ID: 39616

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