Analog Mixed-Signal Power Design Engineer

 

The Role:

We are seeking a senior Analog Mixed Signal design engineer to join the LDO (low drop out regulators) /Power Management design team. This is an excellent opportunity to be part of a team responsible for defining, specifying, and implementing innovative power management solutions for AMD’s compute, graphics and gaming products.

 

The Person:

We are looking for a candidate with validated knowledge and experience in the following areas.

• Has extensive knowledge of voltage regulators, supply monitors, temperature monitors, and other power management, analog and mixed-signal circuits
• Has excellent detailed oriented analytical and problem-solving skills
• Is a self-starter, able to drive tasks independently and efficiently to completion
• Has strong and effective communication skills
• Has ability to provide mentorship and guidance to junior engineers

 

Key Responsibilities:

In this role you will:

• Design/Implement various voltage regulators, supply monitors, temperature monitors, frequency monitors and other power management, analog and mixed-signal circuits
• Deliver detailed specifications and documentation
• Develop circuit schematics and working with layout designers to drive designs to completion (including physical verification and backend/reliability flows)
• Drive design and layout reviews to ensure quality of work you\'re doing and mitigate overall risk
• Work closely with various fields (e.g. Layout, Logical Design, Physical Design, Firmware, and Design Verification) to ensure successful cross-team engagement and high-quality execution
• Document and summarize design and simulation results and hosting well organized design reviews
• Performing pre-Tapeout electrical check tools including EMIR/SigEM (signal electro migration), Logical Equivalence, Electrical Static Discharge compliance, etc.

 

Preferred Experience:

• Experience with Cadence Spectre simulator and/or HSPICE
• Experience with voltage regulators and voltage reference designs
• Experience with Cadence schematic entry and layout tools
• Familiarity with package resonance on silicon design
• Experience with integration of power management systems in large SOCs
• Experience with High Current (>1 A) designs
• Familiarity with deep sub-micron FINFET CMOS processes and second order effects that affect sub-micron silicon processes (e.g. NBTI/PBTI, hot-electron, etc.)
• Familiarity with Logical Equivalence Check, Totem, Electrical Static Discharge Perc, Spicecheck, and System Verilog
• Familiarity with Unix/Linux environments, Perl, Python, and/or MATLAB

 

Academic Credentials:

• Masters or PHD in Electrical or Computer Engineering